Vivado Synthesis Decision Guide

Based on UG901 (v2025.2). This skill helps choose the right synthesis strategies, options, and attributes. For attribute syntax see REFERENCE.md; for HDL coding templates (RAM/DSP/ROM/SRL/FSM/etc.) see examples/ directory — consult the index table in REFERENCE.md to locate the right file.

synth_design Complete Options

Hierarchy Control

Timing Optimization

Resource Control

FSM & Logic

Clock & IO

Design Entry

Special Modes

Debug & Performance

Multi-Threading

set_param general.maxThreads 8  ;# 1-8 threads for synthesis

Strategy Decision Table

Use -directive <strategy> to select:

Note: Directive values are case-sensitive in v2025.2. Use exactly as shown above.

Synthesis Attributes Quick Reference (by scenario)

Preventing Optimization

Resource Inference Control

Timing Optimization

Debug

FSM

IO & Clock

Enable & Reset

DSP Folding

Verilog Case Control

Other

Block-Level Synthesis (BLOCK_SYNTH)

Apply per-instance synthesis settings via XDC:

set_property BLOCK_SYNTH.<option> <value> [get_cells <instance>]

Note: BLOCK_SYNTH hardens the instance hierarchy. Use only where needed.

OOC (Out-of-Context) Synthesis

When to use: Large IP modules, 3rd-party netlists, modules that rarely change.

# Non-Project Mode
synth_design -top <module> -part <part> -mode out_of_context

# Project Mode: right-click module → Set As Out-of-Context for Synthesis

Key rules:
- OOC modules are synthesized independently, treated as black boxes in top-level synthesis
- No IO buffers are created
- Incremental synthesis is NOT supported for OOC runs
- Do NOT use OOC if module has AMD IP in lower levels
- Do NOT use OOC if module ports use user-defined types

Incremental Synthesis

Detects RTL changes and only re-synthesizes modified sections. Reduces runtime and QoR fluctuation.

# Project Mode: Settings → Synthesis → Incremental synthesis
# Non-Project Mode:
synth_design -top <top> -part <part> -incremental_mode default

Note: Not supported for OOC runs.

RTL Linter

Pre-synthesis code quality check:

synth_design -lint -top <top> -part <part>
# For OOC runs:
synth_design -lint -srcset [get_property SRCSET [get_runs my_IP_core_synth_1]]

Key rules detected: latch inference (INFER-1), combinational loops (INFER-4), arithmetic overflow (ASSIGN-1), mixed clock edges (CLOCK-1), mixed async resets (RESET-1), unconnected ports (ASSIGN-12). See REFERENCE.md for complete rule table.

Waivers:

create_waiver -type LINT -id ASSIGN-1 -rtl_hierarchy x/y
write_waivers -type LINT -file waivers.tcl

Synthesis-Stage Constraints

Only these constraints are used during synthesis:

Important: Timing analysis on synthesized design uses estimated routing delays — only post-route timing is accurate.

Attribute Propagation Rules

• Placing attribute on a hierarchy affects only its boundary, NOT signals inside (except: DSP_FOLDING, RAM_STYLE, ROM_STYLE, SHREG_EXTRACT, USE_DSP — these DO affect internal signals)
• If same attribute is set in both RTL and XDC with different values → XDC wins
• KEEP must be set in RTL; XDC does not support it.
• DONT_TOUCH supports both RTL and XDC. Set it in RTL when the object may be optimized away before XDC is read. For existing applicable cells or nets, XDC can set or override the property without requiring an RTL edit. Preserve the user's requested modification scope.