Vivado Simulation Decision Guide

Based on UG900 (v2025.2). For complete command syntax and property tables, see REFERENCE.md.

Simulation Flow Overview

RTL + Testbench ──→ Behavioral Sim (functional verification, fastest)
       ↓ synth_design
Synthesized Netlist ──→ Post-Synth Sim (synthesis correctness, optional)
       ↓ place_design + route_design
Implemented Netlist + SDF ──→ Timing Sim (timing verification, slowest)
       ↓
SAIF/VCD ──→ report_power (power analysis)

Three Simulation Stages

When to Use Each Stage

• Daily development → Behavioral sim only
• Functional mismatch after synthesis → Post-synthesis sim to isolate
• Timing closure verification → Post-implementation timing sim
• Power estimation → Any stage + SAIF dump → report_power

Vivado Simulator (xsim) — Project Mode

Recommended for interactive development with Vivado GUI/project.

# Configure simulation settings
set_property -name {xsim.simulate.runtime} -value {1000ns} -objects [get_filesets sim_1]
set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]
set_property -name {xsim.elaborate.debug_level} -value {typical} -objects [get_filesets sim_1]

# Launch behavioral simulation
launch_simulation
run 100ns
close_sim

Simulation Modes in Project Mode

launch_simulation -mode behavioral          ;# RTL sim (default)
launch_simulation -mode post-synthesis -type functional   ;# Post-synth functional
launch_simulation -mode post-synthesis -type timing       ;# Post-synth timing
launch_simulation -mode post-implementation -type functional  ;# Post-impl functional
launch_simulation -mode post-implementation -type timing      ;# Post-impl timing

Generate Scripts Without Running

launch_simulation -scripts_only             ;# Generate sim scripts only
launch_simulation -scripts_only -absolute_path  ;# With absolute paths

Vivado Simulator (xsim) — Non-Project Mode (Scripted)

Three-step flow: Compile → Elaborate → Simulate

# Step 1: Compile
exec xvlog design.v tb.v                    ;# Verilog
exec xvlog -sv design.sv                    ;# SystemVerilog
exec xvhdl design.vhd                       ;# VHDL
exec xvhdl -2008 design.vhd                 ;# VHDL-2008

# Step 2: Elaborate (link)
exec xelab -debug typical tb_top -s sim_snap

# Step 3: Simulate
exec xsim sim_snap -runall
exec xsim sim_snap -t run.tcl               ;# With TCL script
exec xsim sim_snap -gui                     ;# With GUI

xelab Debug Level Decision

xelab Key Options

xsim Runtime / Debug Commands

add_force Examples

# Constant force
add_force clk 0
# Clock pattern: 0 at 0ns, 1 at 5ns, repeat every 10ns
add_force clk {0} {1 5ns} -repeat_every 10ns
# Reset pulse: 1 at 0ns, 0 at 100ns
add_force rst {1} {0 100ns}
# With radix
add_force -radix hex data_in 0xFF

Timing Simulation (Post-Implementation)

Netlist Generation

# Post-synthesis functional netlist
open_checkpoint post_synth.dcp
write_verilog -mode funcsim -force post_synth_func.v

# Post-implementation timing netlist + SDF
open_checkpoint post_route.dcp
write_verilog -mode timesim -sdf_anno true -force post_impl_timing.v
write_sdf -force post_impl_timing.sdf

# VHDL variants
write_vhdl -mode funcsim -force post_synth_func.vhd

write_verilog -mode Options

SDF Back-Annotation

xelab handles SDF automatically when -sdf_anno true is used in write_verilog:

# xelab with timing simulation netlist
exec xelab -debug typical tb_top glbl \
    -transport_int_delays \
    -pulse_r 0 -pulse_e 0 \
    -s timing_sim_snap

For manual SDF specification:

exec xelab -debug typical tb_top glbl \
    -sdfroot /tb_top/uut \
    -transport_int_delays \
    -pulse_r 0 -pulse_e 0 \
    -s timing_sim_snap

Process Corner Selection

write_sdf -process_corner fast -force fast_corner.sdf   ;# Best case
write_sdf -process_corner slow -force slow_corner.sdf   ;# Worst case (default)

glbl.v Requirements

Path: $XILINX_VIVADO/data/verilog/src/glbl.v

# Include glbl.v in compilation and elaboration
exec xvlog $::env(XILINX_VIVADO)/data/verilog/src/glbl.v
exec xelab tb_top glbl -debug typical -s sim_snap

Third-Party Simulator Integration

Supported Simulators

Step 1: Compile Simulation Libraries (One-Time)

compile_simlib -simulator questa -directory /path/to/compiled_libs \
    -family all -language all

Step 2: Set Target Simulator

set_property target_simulator Questa [current_project]
# Or: ModelSim, VCS, Xcelium, Riviera, ActiveHDL

Step 3: Export Simulation Scripts

# Option A: export_simulation (flexible, supports Non-Project)
export_simulation -simulator questa -directory ./sim_scripts \
    -use_ip_compiled_libs

# Option B: launch_simulation -scripts_only (Project Mode only)
launch_simulation -scripts_only

export_simulation vs launch_simulation -scripts_only

SAIF/VCD Power Simulation

SAIF Collection (Recommended for report_power)

# During simulation (xsim)
open_saif /path/to/output.saif
log_saif [get_objects -r *]       ;# Or specific hierarchy
run 1000ns
close_saif

# Power analysis
open_checkpoint post_route.dcp
read_saif /path/to/output.saif
report_power -file power.rpt

VCD Collection

open_vcd /path/to/output.vcd
log_vcd [get_objects -r *]
run 1000ns
close_vcd

SAIF vs VCD

Simulation Properties Quick Reference

# Runtime
set_property -name {xsim.simulate.runtime} -value {1000ns} -objects [get_filesets sim_1]

# Log all signals
set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]

# Debug level: typical | all | off
set_property -name {xsim.elaborate.debug_level} -value {typical} -objects [get_filesets sim_1]

# Additional xsim options
set_property -name {xsim.simulate.xsim.more_options} -value {-testplusarg FAST} -objects [get_filesets sim_1]

# Additional xelab options
set_property -name {xsim.elaborate.xelab.more_options} -value {-mt 4} -objects [get_filesets sim_1]

# Waveform database file
set_property -name {xsim.simulate.wdb} -value {my_sim.wdb} -objects [get_filesets sim_1]

# Target simulator
set_property target_simulator Questa [current_project]

Simulation Fileset Management

# Add simulation source
add_files -fileset sim_1 tb_top.v

# Set top module
set_property top tb_top [get_filesets sim_1]

# Set top library
set_property top_lib work [get_filesets sim_1]

# Create additional sim fileset
create_fileset -simset sim_2

Language Support