Vivado Implementation Decision Guide

Based on UG904 (v2025.2). For command syntax and property tables see REFERENCE.md; for report_qor_suggestions RTL optimization examples (UG906 before/after) see examples/ug906/ directory.

Implementation Flow Overview

opt_design          ← Logic optimization (REQUIRED)
  ↓
power_opt_design    ← Clock gating power opt (OPTIONAL, not Versal)
  ↓
place_design        ← Placement (REQUIRED)
  ↓
power_opt_design    ← Post-place power opt (OPTIONAL)
  ↓
phys_opt_design     ← Post-place physical opt (OPTIONAL, recommended)
  ↓
route_design        ← Routing (REQUIRED)
  ↓
phys_opt_design     ← Post-route physical opt (OPTIONAL)
  ↓
write_bitstream     ← Bitstream (all except Versal)
write_device_image  ← Device image (Versal only)

Key rule: All implementation commands are re-entrant — they can be run repeatedly on the same design. Each run optimizes the results of the previous run.

opt_design — Logic Optimization

Directive Decision Table

Available Optimizations (18 phases)

IMPORTANT: Specifying individual options disables ALL default options. To run defaults + extras: opt_design -retarget -propconst -sweep -bufg_opt -shift_register_opt -bram_power_opt -remap

place_design — Placement

Directive Decision Table

Key Options

phys_opt_design — Physical Optimization

Two Modes

• Post-place: More aggressive, based on placement timing estimates
• Post-route: More conservative, uses actual routed delays, auto-updates routing

TIP: Post-route phys_opt is most effective on designs with few failing paths (WNS > -0.200 ns). Designs with > 200 failing endpoints see little improvement.

Directive Decision Table

Key Individual Options

Setup optimization (post-place defaults):
| Option | Description |
|--------|-------------|
| -fanout_opt | Replicate high-fanout net drivers (default post-place) |
| -critical_cell_opt | Replicate cells in failing paths (default post-place) |
| -placement_opt | Re-place critical path cells (default both modes) |
| -dsp_register_opt | Move registers in/out of DSP cells |
| -bram_register_opt | Move registers in/out of BRAM cells |
| -uram_register_opt | Move registers in/out of UltraRAM cells |
| -shift_register_opt | Extract SRL end stages to improve timing |
| -restruct_opt | Swap LUT connections to reduce logic levels |
| -lut_opt | Single LUT movement/replication |
| -clock_opt | Useful clock skew optimization |

Routing optimization (post-route defaults):
| Option | Description |
|--------|-------------|
| -routing_opt | Re-route critical nets/pins (default post-route) |
| -slr_crossing_opt | Optimize inter-SLR paths (default both modes) |
| -critical_pin_opt | Remap LUT pins to faster physical pins |

Hold fixing:
| Option | Description |
|--------|-------------|
| -hold_fix | Fix hold violations above threshold |
| -aggressive_hold_fix | Fix more hold violations |
| -sll_reg_hold_fix | SLL register hold fix (UltraScale+) |
| -insert_negative_edge_ffs | Insert neg-edge FFs to split hold paths |

Other:
| Option | Description |
|--------|-------------|
| -retime | Register retiming (Versal) |
| -interconnect_retime | Interconnect retiming by FF movement (Versal) |
| -force_replication_on_nets <nets> | Force driver replication on specific nets |
| -equ_drivers_opt | Rewire loads to equivalent drivers |
| -casc_opt | LUT cascade optimization (Versal) |
| -cell_group_opt | Critical fanin cone group opt (Versal) |
| -bram_enable_opt | Reverse BRAM power opt on timing-critical enable paths |
| -path_groups <args> | Limit optimization to specific path groups |
| -tns_cleanup | Allow slack degradation if WNS maintained (with -slr_crossing_opt) |

route_design — Routing

Directive Decision Table

Key Options

Pre-routing Critical Nets Pattern

# Route top 10 critical nets first with minimum delay
set preRoutes [get_nets -of [get_timing_paths -max_paths 10]]
route_design -nets [get_nets $preRoutes] -delay
# Then route rest preserving critical routes
route_design -preserve

power_opt_design — Power Optimization

# Basic usage (optimize entire design)
power_opt_design

# Control scope
set_power_opt -include_cells [get_cells inst_A]
set_power_opt -exclude_cells [get_cells inst_B]
set_power_opt -cell_types {BRAM}
set_power_opt -clocks {clk1}

Note: Not supported for Versal. BRAM power opt is skipped if already done by opt_design.

Incremental Implementation

Setup

# Non-Project Mode
read_checkpoint -incremental <reference_routed.dcp>
# Automatic incremental (recommended)
read_checkpoint -incremental -auto_incremental <reference.dcp>
# Force incremental even if criteria not met
read_checkpoint -incremental -force_incr <reference.dcp>
# Fix specific objects
read_checkpoint -incremental <ref.dcp> -fix_objects [all_rams]

Incremental Directives

read_checkpoint -incremental -directive <directive> <ref.dcp>

Auto Incremental Criteria

• Cell matching ≥ 94%
• Net matching ≥ 90%
• Reference WNS ≥ -0.250 ns

Analysis

report_incremental_reuse -file incr_reuse.rpt

Note: Not supported for Versal.

Congestion Analysis & Resolution

Congestion Levels

• Level 5 (32x32 tiles) — warning threshold, expect timing impact
• Level 8+ — router early exit, design likely unroutable

Diagnosis

report_design_analysis -congestion -file congestion.rpt
report_route_status -file route_status.rpt

Resolution Decision Tree

1. Synthesis: Use AlternateRoutability directive, reduce MUXF/CARRY usage
2. opt_design: Use -muxf_remap, -carry_remap, LUT_DECOMPOSE property
3. place_design: Use AltSpreadLogic_high or SSI_SpreadLogic_high
4. route_design: Use AlternateCLBRouting
5. RTL changes: Reduce fanout, pipeline long paths, reduce resource utilization

Predefined Implementation Strategies (Project Mode)

Performance-focused

Performance_Auto_1/2/3, Performance_Explore, Performance_ExplorePostRoutePhysOpt, Performance_ExploreWithRemap, Performance_WLBlockPlacement, Performance_WLBlockPlacementFanoutOpt, Performance_EarlyBlockPlacement, Performance_NetDelay_high/low, Performance_Retiming, Performance_ExtraTimingOpt, Performance_RefinePlacement, Performance_SpreadSLLs, Performance_BalanceSLLs, Performance_BalanceSLRs, Performance_HighUtilSLRs

Congestion-focused

Congestion_SpreadLogic_high/medium/low, Congestion_SSI_SpreadLogic_high/low

Area-focused

Area_Explore, Area_ExploreSequential, Area_ExploreWithRemap