Vivado Design Analysis & Timing Closure Guide

Based on UG906 (v2025.2). This skill helps interpret analysis reports and make timing closure decisions. For complete command syntax, see REFERENCE.md. For TCL execution, use vivado-tcl. For constraint changes, use vivado-constraints. For implementation strategies, use vivado-impl.

Timing Path Fundamentals

Four common path types:

1. Input Port → Register       (constrained by set_input_delay)
2. Register → Register         (constrained by clock period)
3. Register → Output Port      (constrained by set_output_delay)
4. Input Port → Output Port    (combinational, set_max_delay)

Path structure (three sections):

Source Clock Path → Data Path → Destination Clock Path
(clock source      (launch pin    (clock source
 to launch cell)    to capture     to capture
                    cell input)    cell)

Slack formula:
- Max delay (Setup/Recovery): slack = data_required_time - data_arrival_time
- Min delay (Hold/Removal): slack = data_arrival_time - data_required_time

Max/Min Delay Analysis Corner Selection

Key rule: Delays from different corners are NEVER mixed on same path during slack calculation.

Report Selection Guide

Timing Report Header Fields

Clock Uncertainty Components

Delay Type in Path Details

Clock Phase Shift Mode (Device Defaults)

Warning: Migrating 7 Series/UltraScale designs to UltraScale+ changes phase shift modeling. Review and remove legacy multicycle path constraints used for phase shift.

QoR Assessment Interpretation (report_qor_assessment)

Score Meaning

Five Assessment Categories

Each shows OK or REVIEW status. Items with asterisk (*) don't directly affect score but impact closure.

A QoR score predicts closure likelihood; it does not replace checks on the final design. For closure requests, use the full timing acceptance criteria, including constraint coverage and applicable bus-skew, CDC, DRC, and methodology checks. For report-only requests, explain the evidence and any verification gaps without automatically starting implementation or bitstream generation.

ML Strategy Availability

Available when ALL conditions met:
- opt_design ran with Explore or Default directive
- phys_opt_design enabled
- Design fully routed
- UltraScale or UltraScale+ device family

Auto-Termination

Set MIN_RQA_SCORE property (1-5) to auto-terminate runs scoring below threshold.

QoR Suggestions Workflow

report_qor_suggestions          ← Generate suggestions
        ↓
write_qor_suggestions file.rqs  ← Export to file
        ↓
read_qor_suggestions file.rqs   ← Import in next run
        ↓
Suggestions auto-apply          ← If AUTOMATIC=Yes

Suggestion Classification

Suggestion Categories

Clocking, Congestion, Utilization, Timing, Netlist, XDC, Strategy

Design Analysis Interpretation (report_design_analysis)

Timing Path Characteristics — Five Categories

Complexity (Rent Exponent) Interpretation

Average Fanout: < 4 normal, 4-5 placement difficulty, > 5 implementation failure risk.

Congestion Level Interpretation

Timing Closure Decision Tree

Setup Violation Resolution

Setup violation detected
  ├─ Check Logic Levels (report_design_analysis)
  │   └─ High logic levels → Pipeline registers / retiming (vivado-synth: -global_retiming)
  ├─ Check Fanout (report_design_analysis)
  │   └─ High fanout → MAX_FANOUT attribute / phys_opt replication (vivado-impl)
  ├─ Check Physical Spread (report_design_analysis -congestion)
  │   └─ Large bounding box → Pblock floorplanning (vivado-constraints)
  ├─ Check Clock Skew
  │   └─ Negative skew → Review clock tree, BUFG placement
  └─ Check Timing Exception
      └─ Missing/wrong constraint → Fix in XDC (vivado-constraints)

Hold Violation Resolution

Hold violation detected
  ├─ Check fast-corner delay
  │   └─ Very short data path → Add delay cells (phys_opt_design hold fix)
  ├─ Check Clock Skew
  │   └─ Large positive skew → Review clock tree balance
  └─ Check Inter-SLR paths (SSI devices)
      └─ SLR crossing → SLR-aware placement (vivado-impl)

Congestion Mitigation

Congestion Level ≥ 5
  ├─ Check utilization (report_utilization)
  │   └─ > 80% LUT → Reduce design size or use area-optimized synthesis
  ├─ Check high-fanout nets
  │   └─ Replicate drivers (phys_opt_design fanout optimization)
  ├─ Try congestion-focused strategies
  │   └─ vivado-impl: Congestion_* strategies
  └─ Floorplanning
      └─ Spread logic across device (Pblocks, vivado-constraints)

Message Severity Levels

Tip: Promote warning severity: set_msg_config -id "Common 17-81" -new_severity "CRITICAL WARNING"

Design Check Waiver System

When to Waive

• Known-safe CDC crossings with external synchronization
• DRC checks not applicable to your design
• Methodology checks overridden by design intent

Waiver Wildcards

Waivers auto-saved in checkpoints. Export with write_waivers, import with read_xdc or source.

Cannot delete AMD IP waivers.

Synthesis Analysis & Closure Techniques

RTL Optimization: Integer Range Constraints

Explicitly define signal ranges to reduce logic depth:

// Before: 32-bit counter, deep comparator logic
reg [31:0] counter;
// After: range-constrained, smaller comparator
reg [9:0] counter;  // if max value < 1024

Deep Memory Decomposition

RAMB Utilization (Non-Power-of-2 Depth)

When memory depth is not a power of 2, synthesis may over-allocate BRAMs. Manually partition with address decoder for optimal utilization. Check report_utilization and synthesis log for memory mapping.

RAMB Output Register Inference

Multiple logic levels before BRAM output flip-flop prevent DOA register inference → timing degradation. Restructure RTL to allow BRAM output register usage (see vivado-impl examples/ug906/ for before/after).

Configurable Report Strategies